ASSASSIN : a CAD system for self-timed control-unit design

technical reportMany software systems exist for automatically implementing synchronous state machines . Presented is this paper is a software system -- ASSASSIN -- for the design and automatic layout of self-timed (or speed- independent) control units as integrated circuit modules

Cascade: a hardware alternative to bignums

technical reportThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation of the greatest common divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascadei hardware permits free tradeoffs of space versus time

Cascade: hardware for high/variable precision arithmetic

technical reportThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation of the greatest common divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascade hardware permits free tradeoffs of space versus time

The path programmable logic (PPL) user's manual

Journal ArticleThis manual describes the primitive NMOS path programmable logic cells currently in use at the University of Utah. It contains detailed descriptions, schematics and composite layout of all cells. Also included are PPL programming rules as well as layout design rules for each cell set

Path-programmable logic

Journal ArticlePath-Programmable Logic (PPL) is a structured IC design methodology under development at the University of Utah. PPL employs a sea-of-wires approach to design. In PPL, design is done entirely using cells for both functionality and interconnect. PPL cells may have modifiers that change either their connections or functionality. Wires in the PPL design plane are segmentable at any cell boundary. PPL is implemented as a set of cell libraries (NMOS, CMOS, and GaAs) and a suite of tools that permit the designer to create, modify, simulate and check PPL circuit designs and to generate mask data for them. PPL exhibits little or no area penalty with respect to full custom densities while permitting system design to be done more rapidly than with gate arrays or standard cells. PPL may be implemented as a sea-of-gates gate array to provide fast turnaround

The set theory of arithmetic decomposition

Journal ArticleThe Set Theory of Arithmetic Decomposition is a method for designing complex addition/ subtraction circuits at any radix using strictly positional, sign-local number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation. The order in which and weight at which each operator is applied maps directly to a physical implementation, including both multiple-level logic and connectivity. The method is readily automated and has been used to design some higher radix arithmetic circuits. It is possible to compute the cost of a given adder before the detailed design is complete

Radix-16 signed-digit division

Journal ArticleFor use in the context of a linearly scalable arithmetic architecture supporting high/variable precision arithmetic operations (integer or fractional), a two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm uses two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit.The algorithm requires a two digit estimate of the (initial) partial remainder and a three digit estimate of the divisor to correctly select each successive quotient digit. The normalization of redundant signed-digit numbers requires accommodation of some fuzziness at one end of the range of numeric values that are considered normalized. A set of general equations for determining the ranges of normalized signed-digit numbers is derived. Another set of general equations for determining the precisions of estimates of the divisor and dividend required in a limited precision SRT model signed-digit division are derived. These two sets of equations permit design tradeoff analyses to be made with respect to the complexity of the model division. The specific case of a two-stage radix-16 signed-digit division is presented. The staged division algorithm used can be extended to other radices as long as the signed-digit number representation used has certain properties

Cell matrix methodologies for integrated circuit design

Journal ArticleA class of integrated circuit design and implementation methodologies is described. These techniques are unique in that they simultaneously model both function and interconnect using cells. These cells are designed such that cell adjacency normally implies interconnection. The absence of an interconnection is explicitly modeled as a wire break between adjacent cells. These methodologies have the potential to greatly simplify and shorten the design process since some design steps are either eliminated or merged with others. They permit near custom layout density while reducing design time over full custom design by up to thirty times and over gate array design by up to four times

RRx-001 in Refractory Small-Cell Lung Carcinoma: A Case Report of a Partial Response after a Third Reintroduction of Platinum Doublets.

RRx-001 is a pan-active, systemically nontoxic epigenetic inhibitor under investigation in advanced non-small cell lung cancer, small-cell lung cancer and high-grade neuroendocrine tumors in a Phase II clinical trial entitled TRIPLE THREAT (NCT02489903), which reexposes patients to previously effective but refractory platinum doublets after treatment with RRx-001. The purpose of this case study is first to report a partial response to carboplatin and etoposide in a patient with small-cell lung cancer pretreated with RRx-001, indicating episensitization or resensitization by epigenetic mechanisms, and second to discuss the literature related to small-cell lung cancer and episensitization